library ieee;
use ieee.std_logic_1164.all;

entity reg60 is

Port(
	clk	: in std_logic;
	rst	: in std_logic;
	wr : in std_logic;
	data_in : in std_logic_vector(59 downto 0);
	data_out : out std_logic_vector(59 downto 0)
);

end reg60;



architecture Behavioral of reg60 is

	signal data : std_logic_vector(59 downto 0);
	
begin
	data_out <= data;
	
	process(clk,rst)
	begin
	if rst = '1' then
		data <= "000000000000000000000000000000000000000000000000000000000000";
	else
		if clk'event and clk = '1' then
			if wr = '1' then
				data <= data_in;
			end if;
		end if;
	end if;
	end process;


end Behavioral;